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SNAP HOME > STAFF > ANDREW DEMPSTER'S PUBLICATIONS


Andrew Dempster's Publications

Ordered by date, latest first

  1. E.P. Glennon & A.G. Dempster, 2004. A review of GPS cross correlation mitigation techniques, Proc 2004 Int. Symp. on GNSS/GPS, Sydney, Australia, 6-8 December. (Download PDF)
  2. A.G. Dempster, 2004. New GNSS signals: Receiver design challenges, Proc 2004 Int. Symp. on GNSS/GPS, Sydney, Australia, 6-8 December. (Download PDF)
  3. A.G. Dempster, 2004. Aperture jitter effects in software radio GNSS receivers, Proc 2004 Int. Symp. on GNSS/GPS, Sydney, Australia, 6-8 December. (Download PDF)
  4. A.G. Dempster, M.D. Macleod & O. Gustafsson, Comparison of graphical and sib-expression elimination methods for design of efficient multipliers, Proc Asilomar Conference on Signals, Systems, & Computers, Monterey, California, 7-9 November 2004.
  5. O. Gustafsson, J.O. Coleman, A.G. Dempster & M.D. Macleod, Low complexity hybrid form FIR filters using matrix multiple constant multiplication, Proc Asilomar Conference on Signals, Systems, & Computers, Monterey, California, 7-9 November 2004.
  6. S.S. Demirsoy, A.G. Dempster & I. Kale, Efficient imlementation of digital filters using novel reconfigurable multiplier blocks (ReMB), Proc Asilomar Conference on Signals, Systems, & Computers, Monterey, California, 7-9 November 2004.
  7. F.B. Tek, A.G.Dempster & I. Kale, Noise sensitivity of watershed segmentation for different connectivity: experimental study, Electronics Letters, 40(21), 1332-1333.
  8. A.G. Dempster & M.D. Macleod, Generation of signed-digit representations for integer multiplication, IEEE Signal Processing Letters, 11(5), 2004, 663-665.
  9. M.D. Macleod & A.G. Dempster, Common subexpression elimination algorithm for low-cost multiplierless implementation of matrix multipliers, Electronics Letters, 40(11), 2004, 651-652.
  10. A.G. Dempster & M.D. Macleod, Using all signed-digit representations to design single integer multipliers using subexpression elimination, Proc ISCAS 2004, 24-26 May 2004, Vancouver, Canada.
  11. A.G. Dempster & M.D. Macleod, Digital filter design using subexpression elimination and all signed-digit representations, Proc ISCAS 2004, 24-26 May 2004, Vancouver.
  12. O. Gustafsson, A.G. Dempster & L. Wanhammer, Multiplier blocks using carry-save adders, Proc ISCAS 2004, 24-26 May 2004, Vancouver, Canada.
  13. K. Johansson, O. Gustafsson, A.G. Dempster & L. Wanhammar, Algorithm to reduce the number of shifts and additions in multiplier blocks using serial arithmetic, 12-14 May 2004, Dubrovnic, Croatia.
  14. R.C. Bryant, E.P. Glennon, A.G. Dempster & S.L. Dougan, Satellite-based positioning system receiver for weak signal operation, Patent granted: United States 6,642,884 (November 4 2003).
  15. A.G. Dempster, O. Gustafsson & J.O. Coleman, Towards an algorithm for matrix multiplier blocks, Proc ECCTDâ03, Krakow, Poland, Sept 2003, III9-12.
  16. S.S. Demirsoy, R. Beck, A.G. Dempster & I. Kale, Reconfigurable implementation of recursive DCT kernels for reduced quantization noise, Proc ISCAS 2003, Bangkok, Thailand, May 2003, IV289-292.
  17. S.S. Demirsoy, A.G. Dempster & I. Kale, Design guidelines for reconfigurable multiplier blocks, Proc ISCAS 2003, Bangkok, Thailand, May 2003, IV293-296.
  18. K.N.R.Mohana Rao, A.G. Dempster, B. Jarra & S. Khan, Automatic scanning of malaria infected blood slide images using mathematical morphology, IEE seminar on Medical applications of Signal Processing, October 2002, London, UK, 12/1-12/6.
  19. S.S. Demirsoy, A.G. Dempster & I. Kale, Power consumption behaviour of multiplier block algorithms, Proc MWSCAS 2002, Tulsa, Aug 2002.
  20. K.N.R Mohana Rao & A.G. Dempster, Use of area-closing to improve granulometry performance, Proc VIPromCom-2002, Zadar, Croatia, 16-19 June 2002, 295 - 301.
  21. K.N.R. Mohana Rao & A.G. Dempster, Modification on distance transform to avoid over-segmentation and under-segmentation, Proc VIPromCom-2002, Zadar, Croatia, 16-19 June 2002, 295 - 301.
  22. O. Gustafsson, A.G. Dempster & L. Wanhammer, Extended results for minimum-adder constant integer multipliers, Proc ISCAS 2002, Phoenix, Arizona, 27-29 May 2002, I73-76.
  23. S.S. Demirsoy, A.G. Dempster & I. Kale, Power analysis of multiplier blocks, Proc ISCAS 2002, Phoenix, Arizona, 27-29 May 2002, I297-300.
  24. A.G. Dempster, S.S. Demirsoy & I. Kale, Designing multiplier blocks with low logic depth, Proc ISCAS 2002, Phoenix, Arizona, 27-29 May 2002, V773-776.
  25. C. di Ruberto, A.G. Dempster, S. Khan & B. Jarra, Analysis of infected blood cell images using morhological operators, Image and Vision Computing, 20(2), 2002, 133-146.
  26. C. Di Ruberto & A.G. Dempster, Attributed skeleton graphs using mathematical morphology, Electronics Letters , 37(22), 2001, 1325-1327.
  27. R. Beck, A.G. Dempster & I. Kale, Finite-precision Goertzel filters used for signal tone detection, IEEE Trans Circuits and Systems II, 2001, 691-700.
  28. K.N.R Mohana Rao & A.G. Dempster, Area-granulometry: an improved estimator of size distribution of image objects, Electronics Letters, 37(15), 2001, 950-951.
  29. S.S. Demirsoy, R. Beck, A.G. Dempster & I. Kale, Novel recursive DCT implementations: A comparative study, IEEE Int. Conf. on Intelligent Data Acqusition & Advanced Computing Systems (IDAACS'2001), Ukraine, July 2001, 120-123.
  30. C. di Ruberto, A.G. Dempster, S. Khan & B. Jarra, Morphological image processing for evaluating malaria disease, 4th International Workshop on Visual Form, Capri, Italy, May 2001, 739-748.
  31. A.G. Dempster & C. di Ruberto, Using granulometries in processing images of malarial blood, Proc ISCAS 2001, Sydney, Australia, 6-9 May 2001, V291-294.
  32. V.A. Bartlett & A.G. Dempster, Using carry-save adders in low-power multiplier blocks, Proc ISCAS 2001, Sydney, Australia, 6-9 May 2001, IV222-225.
  33. "Satellite Based Positioning System Receiver for Weak Signal Operation", US Patent Application no. 09/851,355, International Patent Application no. PCT/AU02/00064, priority dates both 23 Jan 2001, European patent 02710676.4-2220-AU0200064, filing date 23 Jan 2002.
  34. A.G. Dempster & V.A. Bartlett, Transition reduction in multiplier-block based digital filters, IEE Low Power IC Design Seminar, 19 Jan 2001, 14/1-6.
  35. A.G. Dempster & N.P. Murphy, The binomial window: Heuristics and metrics, Signal Processing, 80(12), 2000, 2641-2645.
  36. S.S. Demirsoy, A.G. Dempster & I. Kale, Transition analysis in multiplier-block based FIR filter structures, IEEE International Conference on Electronic Circuits and Systems (ICECS 2000), Kaslik, Lebanon, Dec 2000.
  37. A.G. Dempster, Graphical design techniques for fixed-point multiplication, VLSI Design, 11(4), 2000, 363-379.
  38. C. Di Ruberto & A.G. Dempster, Circularity measures based on mathematical morphology, Electronics Letters , 36(20), 2000, 1691 -1693.
  39. C. di Ruberto, A.G. Dempster, S. Khan & B. Jarra, Automatic thresholding of infected blood images using granulometry and regional extrema, 15th International Conference of Pattern Recognition (ICPR'2000), Barcelona, Spain, 3-8 Sept 2000, 445-448.
  40. C. di Ruberto, A.G. Dempster, S. Khan & B. Jarra, Segmentation of blood images using morphological operators, 15th International Conference of Pattern Recognition (ICPR'2000), Barcelona, Spain, 3-8 Sept 2000, 401-404.
  41. A.G. Dempster & N.P. Murphy, Efficient filter banks and interpolators, Proc. 4th World Multiconference on Circuits, Systems, Communications and Computers (CSCC 2000), Athens, Greece, July 2000, book 2, 1-6.
  42. R. Beck, A.G. Dempster & I. Kale, Characterisation of finite-precision resonators used in recursive filter DFT implementations, Signal Processing, 80(1), 2000, 161-183.
  43. A.G. Dempster & N.P. Murphy, Efficient interpolators and filter banks using multiplier blocks, IEEE Trans Signal Processing, 48(1), 2000, 257-261.
  44. A.G. Dempster, The hit-or-miss transform - a morphological image correlation, Proc Matlab DSP Conference 1999, November 1999, 78-81.
  45. C. di Ruberto & A.G. Dempster, Morphological processing of malarial slide images, Proc Matlab DSP Conference 1999, November 1999, 82-90.
  46. A.G. Dempster & M.D. Macleod, Graphical methods for efficient multiplier design 1: Theory and algorithms, invited paper, Proc European Conference on Circuit Theory and Design (ECCTD99), September 1999, vol 1, 257-260.
  47. A.G. Dempster & M.D. Macleod, Graphical methods for efficient multiplier design 2: Applications to digital filters, invited paper, Proc European Conference on Circuit Theory and Design (ECCTD99), September 1999, vol 1, 261-264.
  48. A.G. Dempster & N.P. Murphy, Lagrange interpolator filters and binomial windows, Signal Processing, 76(1), 1999, 81-91.
  49. A.G. Dempster & M.D. Macleod, IIR digital filter design using minimum-adder multiplier blocks, IEEE Trans Circuits & Systems II - Digital & Analog Signal Processing, 45(6), 1998, 761-763.
  50. A.G. Dempster & M.D. Macleod, Comments on 'Minimum Number of Adders for Implementing a Multiplier and Its Application to the Design of Multiplierless Digital Filters', IEEE Trans Circuits & Systems II - Digital & Analog Signal Processing, 45(2), 1998, 242-243.
  51. A.G. Dempster & M.D. Macleod, Comparison of fixed-point FIR digital filter design techniques, IEEE Trans Circuits & Systems II - Digital & Analog Signal Processing, 44(7), 1997, 591-593.
  52. A.G. Dempster, The cost of limit-cycle elimination in IIR digital filters using multiplier blocks, Proc International Symposium on Circuits and Systems (ISCAS97), June 1997, vol 4, 2204-2207.
  53. A.G. Dempster & M.D. Macleod, Variable wordlengths in filters with least-squares error criterion, Electronics Letters, 33(3), 1997, 201-202.
  54. A.G. Dempster, Reducing complexity by increasing order of IIR digital filters, Proc. 3rd IEEE Int. Conf. on Electronics, Circuits and Systems, (ICECS 96), Greece, 13-18 October 1996, vol. 1, 522-525.
  55. A.G. Dempster & M.D. Macleod, Variable statistical wordlength in digital filters, IEE Proceedings - Vision, Image & Signal Processing, 143(1), 1996, 62-66.
  56. A.G. Dempster & M.D. Macleod, General algorithms for reduced-adder integer multiplier design, Electronics Letters., 31(21), 1995, 1800-1802.
  57. A.G. Dempster & M.D. Macleod, Use of minimum-adder multiplier blocks in FIR digital filters, IEEE Trans Circuits & Systems II - Digital & Analog Signal Processing, 42(8-9), 1995, 569-577.
  58. A.G. Dempster & M.D. Macleod, Variation of FIR complexity with order, Proc. 38th Midwest Symposium on Circuits and Systems, (MWSCAS), Rio de Janeiro, Brazil, 13-16 August 1995, vol. 1, 342-345.
  59. A.G. Dempster, Digital filter design for low-complexity implementation, PhD Thesis, University of Cambridge, 30 June 1995.
  60. A.G. Dempster & M.D. Macleod, Comparison of IIR filter structure complexities using multiplier blocks, Proc. ISCAS 95, pp. II/858-861, Seattle, Washington, 30 April - 3 May 1995.
  61. A.G. Dempster & M.D. Macleod, Multiplier blocks and the complexity of IIR structures, Electronics Letters, 30(22), 1994, 1841-1842.
  62. A.G. Dempster & M.D. Macleod, Constant integer multiplication using minimum adders, IEE Proceedings - Circuits, Devices & Systems, 141(5), 1994, 407-413.
  63. A.G. Dempster & M.D. Macleod, Use of multiplier blocks to reduce filter complexity, Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS '94), London, UK, 30 May - 2 June 1994, vol. 4, 263-266.
  64. A.G. Dempster & M.D. Macleod, Multiplication by an integer using minimum adders, IEE Colloquium on mathematical aspects of signal processing, Digest no. 1994/034, 11/1-11/4, 10 February 1994.
  65. A.G. Dempster, R.C. Bryant, H. Tagaris & S.L. Dougan, "GPS Receiver", Patent granted: Australia 639308 (11 March 1991), United States 5459473 (17 October 1995), UK 2265063 (12 September 1991), Singapore 9790534-3 (12 September 1991), Canada 2096019 (12 September 1991).
  66. A.G. Dempster & R.C. Bryant, Phase-coherent open-loop GPS receiver concept, International Symposium on Signal Processing and Applications, Gold Coast, Australia, 1990.
  67. R.C. Bryant, A.G. Dempster & S.L. Dougan, An open-loop GPS receiver concept, Fifth Australian National Space Symposium, Canberra, Australia, 1989.
  68. D.N. Bundy & A.G. Dempster, The Lyman spacecraft bus and Australian industry, Fourth Australian National Space Symposium, Adelaide, Australia, 1988.

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