FPGA Page

Field Programmable Gate Array (FPGA)
GNSS Receiver Research

Currently GPS receivers consist of a RF frontend, an Applications Specific Integrated Circuit (ASIC) for signal processing, and a CPU core for higher level functions. Firmware can be loaded into the CPU to change the performance parameters of the receiver. However, design flexibility is very constrained by an ASIC that is 'hardwired' with predefined tracking channels, correlator and control loop characteristics. ASICs are also very expensive to produce, so once they are designed for a particular application and manufactured in a 'chip foundry' there are limited possibilities of varying the baseband processing functions through firmware, e.g., to process different GNSS signals.

Field Programmable Gate Arrays (FPGAs), on the other hand, are an example of "reconfigurable computing technology" that sits between hardware and software, and in fact may carry out some or all of the previously fixed (ASIC) hardware functions. FPGAs are being increasingly used by manufacturers for rapid prototyping of receiver designs, before they are 'cast in silicon' (as ASICs). However, within the next 3-5 years, it is mooted that FPGAs will become the preferred 'silicon' component inside many digital/portable devices. In other words, a FPGA-based GNSS receiver can be both a research tool (as it is reprogrammable, e.g. to incorporate extra processing power or tracking channels, as the need arises), as well as being effectively the final GNSS receiver product. FPGA-based GNSS receivers (& integrated devices) is a new research initiative under Theme 4, under the direction of Assoc. Prof. Andrew Dempster. This web page summarises progress on a number of projects based on FPGAs, as well as providing links to some useful FPGA web sites.

FPGA resource links
FPGA vendor sites
FPGA project: controlling radio communications from multiple tracked objects
FPGA GNSS receiver project: NICTA Pilot Project

FPGA Web Resources

www.fpgajournal.com
www.fpgacentral.com
www.fpgacpu.org
www.mrc.uidaho.edu/fpga/fpga.html
www.klabs.org
www.fpga-faq.com
www.soccentral.com/results.asp?catid=180
www.eg3.com/fpga.htm

FPGA Vendor Sites

www.actel.com
www.atmel.com
www.altera.com
www.cypress.com
www.latticesemi.com
www.lucent.com/micro/netcom/orca/
www.quicklogic.com
www.xilinx.com

Radio Communications for Multiple Tracked Objects

The challenge for graduate student Kevin Parkinson was to develop a system by which multiple objects could be tracked as they moved around a confined area. High precision GPS kinematic positioning was the requirement, but at a server or central site, i.e. the GPS was attached to an object being tracked. Hence the raw GPS data needed to be transmitted to the main computing platform, where the GPS computations were carried out. A FPGA-controlled spread spectrum transmitter was developed. The integrated GPS-datalink 'rover' device was of small size (see below). The entire system was able to track up to 32 rovers, with position of decimetre-level accuracy available at updates of 10Hz at the system server. The project commenced in early-2003. More details, click here ...

The lightweight rover unit, incorporating a CMC Superstar GPS receiver & specially designed FPGA-controlled spread spectrum transmitter. GPS & datalink transmitter antennas shown on box.

FPGA-based GNSS Receiver Design

The National ICT Australia (NICTA) research centre at UNSW and the SNAP Lab launched an initiative in mid-2004 to develop a FPGA-based GPS L1 receiver. Peter Mumford, Andrew Dempster nd Kevin Parkinson were closely associated with this pilot project. The result of the collaboration is the "NAMURU" GPS receiver, the first receiver designed and built by an Australian academic department. The FPGA receiver will be used for subsequent GNSS-based research within the SNAP Lab.

Click here for a paper presented at the International Symposium on GPS/GNSS2004, Sydney, Australia ...

Prototype of FPGA-based receiver using the Altera Development Kit (CMC Superstar connected at bottom right)

First photo of UNSW-designed, FPGA-based receiver board (June 2005)

FPGA-based GPS/INS Integration

The Cooperative Research Centre for Spatial Information has been funding Project 1.3 "Integrated Positioning & Georeferencing Platform" to develop initially an integrated GPS/INS system on the FPGA platform. See the "Multi-Sensor Integration" web site.

Field Programmable Gate Array (FPGA) GNSS Receiver Research