FPGA-based Real-time GPS/INS Integrated System

 

The integration of GPS and INS can overcome the defects of INS or GPS standalone systems, and benefits from the complementary characteristics of the two systems. GPS/INS integration is most often implemented on a PC or application-specific integrated circuit (ASIC) platform. The SNAPlab researchers have successfully developed a far more flexible platform based on field programmable gate array (FPGA) technology. The biggest advantage of the FPGA-based system is that all the hardware and software components of the system are field re-programmable without any hardware changes, with even the processor of the system itself is “soft”. A “hardcopy” FPGA can be made after the system has been sufficiently tested. Compared with the ASIC approach, the FPGA approach can shorten the research and development period. This reprogrammable hardware configuration represents a system design methodology of lower risk. It also allows maximum flexibility, being able to integrate a wide range of GPS and INS sensor packages.

 

The development has been conducted under the Australian Cooperative Research Centre for Spatial Information (CRC-SI) project 1.3 “Integrated Positioning and Geo-referencing Platform”. This project aims to develop a generic hardware/software platform for positioning and imaging sensor integration. Following 3-years of research and development, the following outcomes have been obtained:

 

(1) Software packages for both “tight” and “loose” integration of GPS and INS have been completed. The tight integration system as implemented fuses the INS solution with the GPS pseudorange and Doppler measurements. The loose integration system extends the functionality of the tight integration system to support a broader range of GPS receivers that provide only position output (instead of raw PR and Doppler measurements).

 

(2) An FPGA-based time-sync data logging device has been developed. Time-synchronisation has been demonstrated at an accuracy level of 0.3ms in comparison with Boeing’s C-MIGITS II (best reference). The system records the GPS and INS raw/processed data onto a compact flash card. The data can then be subsequently processed by the tight/loose integration software for estimation of the INS errors.

 

(3) A real-time GPS/INS integrated system has been implemented on the FPGA platform by porting the loose integration software package to the Nios II processor core on the FPGA. It achieves time-synchronisation and performs loose integration calculations in real time. The raw data and the integrated solution are stored in the CF card for replay or post-processing.

 

The Altera Stratix EP1S10 FPGA development board is used in the prototype system. The real-time system is built around the Nios II soft-core on a Stratix EP1s10 device, which is configured with 1MB static RAM (512KB ´ 2), 16MB SDRAM, and 8MB flash memory. The Stratix EP1S10 features 10,570 logic elements and 920KB of on-chip memory (http://www.altera.com). The real-time device is currently configured with four UARTs, two of them for INS and GPS input, and another two for integration result output. The GPS pulse-per-second (PPS) signal is required for the time synchronisation process and is connected to the prototype device via a BNC socket. One output UART is connected to the computer running the GIS, and another is connected to a handheld device that can access the internet. The device has an LCD screen for menu and status information display and four buttons for option selection and operation control.

 

The embedded software is developed using the Nios II integrated development environment (IDE). A special version of eCos – ‘the eCos for Nios II’ provides support of the FAT32 file I/O in Compact Flash (CF) card, multi-task programming, LCD display, and interrupts from UARTs and buttons. The main specifications of the real-time system are listed in Table 1.

 

FPGA

Altera’s Stratix EP1S10

Processor

Nios II

Oscillator

50MHz

SRAM

512KB x 2

SDRAM

16MB

Flash

8MB

Embedded OS

eCos for Nios II, ver5.1.

Interface

one LCD; four Buttons; one CF card slot; four UARTs; one BNC.

GPS

OmniStar-HP8200

INS

C-MIGITS II

 

Table 1. Summary of the real-time system

 

The software is designed in a structure consisting of four threads, which are the user interface (UI), time synchronisation (TS), strapdown INS (SDINS), and Kalman filtering (KF). The low update rate GPS and PPS data are collected in the UI thread, and receiving the high update rate IMU data is assigned to TS thread. The time-sync procedure is active when the GPS, PPS, and IMU are available. The time synchronised data are stored in circular buffers and the SDINS thread picks up the data from the buffers to compute the strapdown inertial solution. The KF thread runs once the GPS and INS data matches in the time. Each thread contains its own context or workspace to perform its operations and a priority level to execute.

 

Static and kinematic tests confirm the stability of the time synchronisation mechanism and the general performance of the device. The Boning’s C-MIGITS II’s timing solutions were used as the reference to evaluate the timing accuracy of the FPGA-based device. The result demonstrates a timing accuracy better than 0.3ms. The data logger has potentially higher accuracy because it can reveal the C-MIGITS II’s 10ms/sec clock drift. Other methods have to be used to evaluate the data logger’s true (higher) accuracy capability. In comparison of the solution derived from the differential carrier phase measurements (of a cm level accuracy), the positional error of the integrated solution has an accuracy of better then 1metre (average = 0.44m, std = 0.97m). The overall performance of the system is satisfied in a real application environment where intensively covered by trees and some GPS signal outages were observed. All main functional modules have demonstrated workability.

 


Fig.1 The hardware of the real-time FPGA-based GPS/INS system        Fig. 2 A screen shot of the post-processing software LCIKFÓ

 

Some related publications:

 

  1. Y. Li, P. Mumford, J. Wang, and C. Rizos (2007) A low-cost field re-configurable real-time GPS/INS integrated system – design and implementation, IGNSS2007, Sydney, 4-6 December 2007.
  2. Y. Li, P. Mumford, J. Wang, and C. Rizos, Development of a GPS/INS Integrated System on the Field Programmable Gate Array Platform, Proceedings of ION GNSS 2006, Forth Worth, Texas, September 26-30, 2006.
  3. Y. Li, P. Mumford, J. Wang, C. Rizos, and W. Ding (2006) Time Synchronisation Analysis of an FPGA based GPS/INS Integrated System, Proceedings of IGNSS 2006, Holiday Inn Surfers Paradise, Australia, 17 – 21 July 2006.
  4. P. Mumford, Y. Li, J. Wang, C. Rizos, and W. Ding (2006) A Time-synchronisation Device for Tightly Coupled GPS/INS Integration, Proceedings of IGNSS 2006 , Holiday Inn Surfers Paradise, Australia, 17 – 21 July 2006.

 

Further Information:

 

If you are interesting in knowing more about this device or cooperating relevant developments, please contact us:

 

Dr. Yong Li

Satellite Navigation and Positioning (SNAP) Lab

School of Surveying and Spatial Information Systems

University of New South Wales

Sydney, NSW 2052, Australia

Tel: 61 2 9385 4173

Fax: 61 2 9313 7493

Email: yong.li@unsw.edu.au